“PCBs have become increasingly densely populated, and accessing pins under packages such as ball grid arrays (BGAs) has been virtually...
“PCBs have become increasingly densely populated, and accessing pins under packages such as ball grid arrays (BGAs) has been virtually impossible,” said Kishore Karnane, product management director, PCB Group, Cadence. “Boundary scan addresses this problem by providing electrical access to compliant integrated components on a PCB using a JTAG chain, but it is also imperative that any errors in the JTAG chain are corrected early. XJTAG DFT Assistant allows engineers to determine whether JTAG chains are correctly connected and terminated during schematic capture, early in the design process.”
Developed by boundary-scan hardware and software tool supplier XJTAG, XJTAG DFT Assistant allows users to detect and correct JTAG errors at the design stage before the PCB is produced, preventing costly re-spins and project delays.
http://www.evaluationengineering.com/cadence-releases-xjtag-dft-assistant-orcad-capture
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